1. Field of the Invention
This invention relates to the field of wireless transceivers, particularly to the integration of a transceiver's passive components.
2. Description of the Related Art
The demand for low-cost, reliable wireless communications continues to increase at a rapid rate, as do the demands on the technologies enabling such communications. Research is being conducted on many fronts to find ways to make the circuitry found inside devices such as cellular phones smaller, cheaper, easier to fabricate, less power-hungry, and more reliable.
A block diagram of the RF/analog and analog/digital (A/D) interface circuitry of a basic transceiver is shown in FIG. 1; the circuitry shown is combined with other components (not shown) to form a complete transceiver. The transmitter (T.sub.x) portion of the transceiver includes digital-to-analog converters (DACs) 10 and 12, low-pass filters 14 and 16 for filtering the outputs of DACs 10 and 12, respectively, and a modulator 18 that performs a frequency conversion on signals received at its inputs and which is driven by a phase-locked loop (PLL) circuit 20 that includes a reference voltage-controlled-oscillator (VCO) and a resonator (tank circuit) 22. The modulator's output is fed to a power amplifier 26, and the amplified output is fed to one side of a transmit/receive (T/R) switch 28, filtered with a bandpass filter 30, and connected to an antenna 34.
The receiver portion (R.sub.x) is connected to the other side of T/R switch 28. Incoming signals are received by antenna 34 and filtered by bandpass filter 30 before being fed to a low-noise amplifier (LNA)/demodulator circuit 42. The output of the circuit's LNA 44 is passed through a bandpass filter 46 before being fed to a demodulator 48 which performs a frequency conversion on the signal received by antenna 34. The demodulator 48 is driven by a PLL circuit 50 which includes a reference VCO and a tank circuit 52. The demodulator output drives an intermediate-frequency automatic gain control (IF AGC) stage 56, with a bandpass filter 58 interposed between the stage's IF amplifier 60 and its AGC circuitry 62. The AGC output is fed to an IF demodulator 64 which is driven by a PLL circuit 66 that includes a reference VCO and a tank circuit 68. The IF demodulator's two outputs are passed through respective low-pass filters 72 and 74 before being fed to respective analog-to-digital converters (ADCs) 76 and 78. DACs 10, 12 and ADCs 76, 78 serve as A/D interface circuitry, with the DAC inputs and ADC outputs connected to other digital transceiver circuitry (not shown).
Current transceivers are implemented using a variety of device technologies. For example, DACs 10 and 12, ADCs 76 and 78, and all other digital baseband transceiver circuitry are typically CMOS circuits. Modulator 18, LNA/demodulator 42, IF/AGC stage 56, and IF demodulator 64 generally use bipolar junction transistors (BJTs). The power amplifier 26 is often fabricated on a gallium arsenide (GaAs) substrate, particularly for a high-power application such as a cellular phone. Bandpass and lowpass filters 14, 16, 30, 46, 58, 72 and 74, as well as tank circuits 22, 52 and 68, and antenna 34, are generally built with discrete components. T/R switch 28 is also typically made from discrete components, or are made from costly, complex PIN diode circuits if integrated. However, the poor efficiency of PIN diode circuits at high frequencies (&gt;900 MHZ) typically limits their use, particularly in battery-powered applications. One design, described in a paper by A. Abidi, et al., "The Future of CMOS Wireless Transceivers", ISSCC97, Paper FA 7.2 (1997), implements all of the above-named components using CMOS components, with the exception of the T/R switches, inductors, capacitors and resonators, the implementation of which still requires discrete components.
Because a variety of technologies must be combined, current transceivers typically use a hybrid packaging scheme. Hybrid packaging generally requires the use of performance-degrading wire bonds between components or individual integrated circuit (I.C.) dies, and a labor-intensive and costly assembly process. Such an assembly is typically larger than is desired, particularly when the limited space and weight requirements imposed on designers of battery-powered handheld devices must be met.